This invention relates generally to a semiconductor memory. More particularly, the present invention relates to a dynamic random access memory (hereinafter referred to as "DRAM") having small cells, stable operation, and having memory cells suitable for higher packing density.
Examples of conventional semiconductor memories are shown in FIGS. 1A to 1D of the accompanying drawings. FIGS. 1A and 1B show the semiconductor memory disclosed in JPA 61-184867 and FIGS. 1C and 1D show the semiconductor memory disclosed in JPA 62-51253. In these prior art references, a capacitor is formed at the lower half of a deep hole while a switching transistor is formed at the upper half of this deep hole, and a word line is then formed to cover a bit line which is connected to a drain of the transistor. Because the word line is formed after the drain is formed, the word line is formed on the drain, and consideration is not taken for higher packing density and the increase in the parasitic capacitance between the word line and the drain.
When the memory cells are arranged in a high density, they are disposed at the points of intersection between the word lines and the bit lines to constitute a so-called "cross-point switch". If the word lines are turned ON under this construction (see FIG. 1B), the signal of the capacitor is applied to all the bit lines to turn them ON so that the arrangement unavoidably becomes an open bit line arrangement. Accordingly, this circuit arrangement cannot accomplish a folded bit line arrangement which, exhibits characteristically low noise and therefor is not sufficient from the aspect of a stable circuit operation.
Furthermore, since the capacitor and the switching transistor is buried in the deep hole bored in the substrate in each of the structures shown in FIGS. 1A and 1C, the continuous portion of the word line is disposed on the substrate, thereby forming a step on the substrate.
Another prior art semiconductor memory is discussed in "1985, IEEE International Electron Devices Meeting, Technical Digest", pp. 714-717.
As a result of studies of these prior art techniques, the inventors of the present invention discovered the following problems.
The semiconductor memory cell shown in FIG. 1C is fabricated first forming the drain of an n.sup.+ region of the switching transistor (to be connected to the bit line) on the surface of an Si substrate. Then the deep hole is bored in such a manner as to penetrate through the drain and thereafter the word line (which is integral with the gate of the switching transistor) is formed at the upper part of this deep hole. This fabrication method produces a device having the following problems.
(1) Unlike ordinary MOS transistors (whose drain is formed in self-alignment with the gate after the gate is formed), the drain is covered with the gate so that the parasitic capacitance between the drain and the gate increases.
(2) Since the drain is covered with the gate, the bit line is formed by extending the n.sup.+ region of the drain of the switching transistor.
(3) Only gate portion of the word line is buried in the hole disposed in the substrate while other portions extend on the substrate. This generates a step and is likely to cause disconnection of a metallization layer to be formed thereon.
These problems impede higher packing density and, consequently, also impede larger scale DRAMs.
Though the fabrication method is different, the structure of the memory cell shown in FIG. 1A also have the above-mentioned problems.